FARANE-Q: Fast Parallel and Pipeline Q-Learning Accelerator for Configurable Reinforcement Learning SoC

This paper proposes a FAst paRAllel and pipeliNE Q-learning accelerator (FARANE-Q) for configurable Reinforcement Learning (RL) algorithm implemented in System on Chip (SoC). The proposed work offers flexibility, configurability, scalability while maintaining computation speed accuracy to overcome the challenges of dynamic environment increasing complexity. method includes Hardware/Software (HW/SW) design methodology SoC architecture achieve flexibility. We also propose joint optimizations algorithm, architecture, implementation obtain optimum (high efficiency) performance, specifically energy area efficiency. Furthermore, we real-time Zynq Ultra96-V2 FPGA platform evaluate functionality with an actual use case smart navigation. Experimental results confirm that FARANE-Q outperforms state-of-the-art works by achieving throughput up 148.55 MSps. It corresponds efficiency 1747.64 MSps/W per agent 32-bit 2424.33 16-bit FARANE-Q. Moreover, other related improvement at least $1.23\times $ designed system maintains error less than 0.4% optimized bit precision more eight fraction bits. processing time notation="LaTeX">$1795\times compared embedded SW executed ARM processor notation="LaTeX">$280\times full software i7 processor. Hence, has potential be used navigation, robotic control, predictive maintenance.